The present invention relates to a serial interface suitable for use in an analog to digital converter and to a converter including such an interface. The interface may be used in other devices as well. In particular, the present invention relates to a compact serial interface which enables multiple analog to digital converters to be controlled via an interface comprising only three or four pins. The present invention also relates to a serial interface for a device, such as an analog to digital converter, which enables operation of the device to be controlled and a xe2x80x9cresult readyxe2x80x9d signal to be asserted using only three pins.
It is desired that analog to digital converters, along with many other semiconductor devices, should be implemented in increasingly compact forms. This effects not only the package size of the integrated circuit, but also the number of connections which must be made to it across a printed circuit board. Reducing the number of connections allows more devices to be populated within a given area of circuit board, or alternatively mitigates the need to go to more complex circuit board technologies such as multi-layered boards. It is also desirable that new devices can offer enhanced functionality over older devices, whilst still being able to operate in legacy modes of operation where they reproduce the functionality of earlier devices. Where a device is to be a direct replacement for an earlier design, it is constrained by the pin configuration of that earlier device and hence any new functionality can only be achieved using the same device pin-out.
According to a first aspect of the present invention, there is provided an analog to digital converter comprising a converter section and an interface section, the interface section having a first input and an output from which a digital word representing the result of the conversion can be read, and wherein in a first mode of operation the output is placed into a predetermined output state to signal that the conversion has been completed, and in which the first mode is selected by placing the first input into a first predetermined state before the conversion is complete.
It is thus possible to provide an analog to digital converter (ADC or A/D converter) which, in a first mode of operation, asserts a xe2x80x9cresult obtainedxe2x80x9d signal on its output pin as soon as the conversion has been completed provided the signal at the first input pin thereof is in a predetermined state.
It will be appreciated by the person skilled in the art that in this mode of operation the first input is acting as a chip select input. The chip select input can be active high or low. Where the input is active low, it is traditional to signify this by placing an xe2x80x9cbarxe2x80x9d over the letters, thus an active low chip select input is designated {overscore (CS)}, or in textural form CSB. Both designations will be used herein.
Advantageously in one embodiment of the invention the first input acts as a chip select input when the first input is in the first predetermined state, and the first input acts to signal that a conversion is to be commenced upon a transition from the first to the second predetermined state.
The A/D converter examines the status of the first input relative to the generation of an internal xe2x80x9cend of convertxe2x80x9d (EOC) signal and outputs a result obtained signal when the conversion is finished if the chip select signal was asserted (active) before the conversion was complete. This mode of operation can be considered as a xe2x80x9cchip select, readyxe2x80x9d mode. If the first input is not in the predetermined state when the conversion is complete then the output remains in a high impedance state until such time as the chip select signal is issued. This can be regarded as a second mode, which for convenience can be referred to as a xe2x80x9cchip select, no-readyxe2x80x9d mode.
Preferably in a further embodiment of an A/D converter, the converter further includes a second input for initiating a conversion.
Advantageously a conversion is started in response to a predetermined transition of a signal applied to the second input.
Preferably the analog to digital converter further comprises a clock input and the conversion result is output from the A/D converter in response to transitions of the clock signal at the clock input between a first and second predetermined state. Advantageously in each complete clock cycle only one bit of the conversion result is output from the A/D converter. Thus a device responsive to the A/D converter can control the rate at which it receives data from the converter.
In a preferred embodiment of the present invention there is provided an analog to digital converter in which the analog to digital converter comprises a first input, a second input and a serial clock input, and wherein following the initiation of a conversion by applying a start of convert signal to the second input the converter examines the status of its first input and the serial clock, and if the first input is in a first predetermined state and the serial clock is in a first predetermined serial clock state, then the analog to digital converter enters a third mode where the output is asserted to a third mode predetermined output state to signal that a conversion has been completed when the conversion has been completed and the first input is in a second predetermined state.
Preferably the third mode predetermined output state is the same signal state as the second predetermined state of the first input.
This has the advantage that multiple A/D converters may be connected in a chained fashion, with the output pin of one A/D converter being connected to the first input of a succeeding A/D converter, and the output of the final A/D converter will only be asserted when each and every one of the converters in the chain has completed its conversion.
Advantageously the A/D converters are asynchronous. In this context, this means that the A/D converters perform their analog to digital conversions on the basis of internally set timings and are not tied to a system clock. This is advantageous when performing high resolution and/or high accuracy conversions since it means that a system clock signal need not be provided to the or each converter. The system clock can, from an A/D converter""s perspective, be regarded as an electrically noisy signal which may leak through the circuitry of the analog to digital converter and degrade the final conversion result in terms of resolution and/or accuracy.
It is thus possible to provide an interface for an analog to digital converter, and an A/D converter having such an interface, wherein in the third mode of operation (which may be referred to as a xe2x80x9cchain, readyxe2x80x9d mode) the A/D converter can indicate when it has finished an analog to digital conversion, and wherein these signals can be chained through a plurality of A/D converters such that a bank of converters gives a single output to a subsequent device.
The provision of a second input which signals when a conversion is to be commenced allows one or more converters to be synchronized.
In a preferred embodiment of the interface, the interface only comprises four pins, these being the first input, a serial clock input, a start of conversion input and a serial output. This compact interface structure means that an analog to digital converter can be implemented within a 3 or 4 pin digital interface.
Advantageously, when a plurality of A/D converters are serially connected in a daisy chained mode, the output of each A/D converter is serially shifted into and buffered by a succeeding A/D converter and subsequently output therefrom. The length of the buffer need only match the width of the conversion result and hence can be easily implemented by a shift register within the A/D converter. The shift register is, advantageously, capable of being parallel loaded with the conversion result of the analog circuit within the converter.
Advantageously the A/D converter is operable in a still further mode of operation wherein the converter does not assert a signal at its output when the conversion has been completed. This mode can be considered as a xe2x80x9cchain, no-readyxe2x80x9d mode.
The xe2x80x9cchain, no-readyxe2x80x9d mode is similar to the xe2x80x9cchain, readyxe2x80x9d mode of operation, but can be instigated by ensuring that the serial clock input to the converter is in a second predetermined state when the start of convert instruction is issued.
When the converters are connected together in a chain, it is necessary to be able to reset all of them. A reset condition may, for example, be defined such that when the first and second inputs are both low, then the output goes low. It follows that in a chain configuration where the converters have a shared convert (second input) line, it is only necessary to be able to reset the first converter. This can be achieved either by tying its first input to ground or by attaching the first input to the second input. Under these configurations, once the second input goes low the output of the first converter goes low. The output of the first converter is connected to the first input of the second converter and hence the second converter becomes reset and its output goes low. This causes the third converter to see the reset condition and hence a reset propagates along the chain.
Advantageously the converter is further programmable, for example, to perform a calibration or to define whether the data should be clocked out on a rising or falling edge of the serial clock. This list of programming functions is only exemplary and should not be considered to be either essential or exhaustive. Advantageously a programming mode can be implemented by truncating a data read sequence from the device. Thus, in order to implement programming, the analog to digital converter is first instructed to perform a conversion. Once the conversion has been completed, the device will expect the data to be read out therefrom. If, for example, the converter is a sixteen-bit converter, then the converter will expect a read cycle to comprise a minimum of sixteen serial clock cycles. The read may comprise more than sixteen clock cycles because the converter may be connected in a daisy chain manner with other converters, but a complete read can never comprise less than sixteen cycles in this example. Thus, if the read is terminated before sixteen clock cycles have been completed, the converter interprets this as a programming instruction. Different functions of the programming may also then be selected by combinations of signals being set to logical high or low states on either of the first input or second input, in combination with various lengths of clock sequences. The programming sequences may be hierarchical such that one programming sequence may merely indicate the nature of a subsequent programming sequence. It is thus possible to provide a programmable analog to digital converter operable in various modes of operation and having a compact serial interface which can be limited to merely three or four pins including the serial clock and serial out pins.
It will be appreciated that the serial interface described herein, although described in the context of an analog to digital converter, is also suitable for use with other devices whose operation is essentially asynchronous.
According to a second aspect of the present invention, there is provided a serial interface for a task performing device wherein the device will complete the task after an unspecified duration but within a predetermined maximum duration, and wherein the serial interface comprises a serial clock input, a serial output and a control input and the interface is arranged such that a first transition of the control input initiates the task and a further transition of the control input prior to completion of the task instructs the serial interface to assert a signal on the serial output once the task has been completed.
Advantageously the serial output can assume a high impedance state (such an arrangement is generally known as a tri-state output) and during the task the serial output is in the high impedance state and once the task has been completed the serial output exits from the high impedance state to assert a signal to indicate that the task has been completed.
Advantageously the output line from the serial interface is tied to a known voltage level via a resistor. It is common practice for the output to be tied to the positive supply rail and hence the resistor is known as a pull-up resistor. However it would equally be possible to tie the output to the low voltage (ground) rail. Once the task has been completed, the output should then drive towards the opposite state to that imposed by the resistor. Thus, if a pull-up resistor is used, the output goes low to indicate that the task has been completed.
Advantageously data can be read from the serial data out pin in response to transitions on the serial clock pin. When the data out pin has also been used to indicate that the results are ready for conversion, it is necessary to assert an instruction to cause the output to remove the ready signal, and place the first output bit of the data on the output.
Advantageously, once all of the data has been read out, the serial output can assume a known condition. This may, for example, be to revert to a high impedance state.
Advantageously the serial interface is operable in a further mode such that, in the absence of a further transition of the control pin before the completion of the task, the serial output assumes a high impedance condition until such time as the further transition on the control pin occurs. Thus the output can remain in a high impedance state even after the conversion has been completed and will remain in this state until such time user or other devices indicate to the serial interface that they wish to receive data from it.